A field-effect transistor (“FET”) generally includes an insulating layer formed on a semiconductor substrate, a polycrystalline silicon gate formed on the insulating layer, a pair of source/drain regions formed in the semiconductor substrate, and a channel region formed below the gate insulating layer and separated by the source/drain regions. In the fabrication of FETs, typical complementary metal-oxide-semiconductor (“CMOS”) techniques include a metallization process to electrically couple source/drain pairs to circuits. The metallization process may include providing a patterned mask layer over the semiconductor substrate to expose a source or drain region formed in the semiconductor substrate. Specifically, an opening is made through the patterned mask layer using conventional lithographic techniques for a later deposition of metal materials such as aluminum or aluminum alloys in the opening. In deep sub-micron CMOS processes, however, due to a higher device density on a semiconductor substrate and a smaller device, integrated circuit devices have been miniaturized. As a result, openings for forming metal contacts have smaller dimensions and become liable to mask misalignment. To alleviate limitations set by mask alignment tolerances, self-aligned contact (“SAC”) techniques are generally used to allow for a less precise alignment of masks.
FIG. 1 shows a cross-sectional view of a conventional FET device 10. Referring to FIG. 1, FET device 10 formed on a semiconductor substrate 12 includes a stacked-gate structure 14, a gate insulating layer 16 formed on semiconductor substrate 12 and disposed under stacked-gate structure 14, a source/drain pair 18 formed in semiconductor substrate 12 and separated apart from each other by a channel region 20, and sidewall spacers 22 surrounding the sidewalls (not numbered) of stacked-gate structure 14. Stacked-gate structure 14 may include a conductively doped polycrystalline silicon gate 24, a refractory metal gate 28, and an interlayer dielectric (“ILD”) 26 to isolate gates 24 and 28. FET device 10 usually also includes a conformal layer 30 of silicon oxide formed over gate insulating layer 16 and stacked-gate structure 14 to serve as a stress buffer layer.
A self-aligned contact (not shown) is then formed after source/drain pair 18 is ion implanted. Conventional methods of forming a self-aligned contact may include providing a dielectric layer 32, for example, an oxide layer, over semiconductor substrate 12, and etching dielectric layer 32, buffer layer 30 and gate insulating layer 16 to expose a source/drain region 18, thereby forming a contact opening 34 for a later deposition of contact metal (not shown). Since dielectric layer 32 and buffer layer 30 are composed of silicon oxide, an etchant used to reduce dielectric layer 32 would also attack buffer layer 30 formed between stacked-gate structure 14 and sidewall spacers 22, resulting in an exposure of metal layer 28 as circled, and causing a short-circuit between exposed metal layer 28 and the contact metal to be filled in contact opening 34.